Campus del Baix Llobregat
 
Projectes oferts

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Tribunals i dates de lectura

Projectes llegits
(2012-2)

DG ENG AERO/SIS TEL

DG ENG AERO/TELEMÀT

DG ENG SISTE/TELEMÀT

ENG TELEC 2NCICLE 01

ET AERO/ETT SIST 05

ET AERONÀUTICA 03

ETT SIST/ ET AERO 05

ETT SIST TELEC 00

ETT SIST TELEC 91

ETT TELEMÀTICA 00

GR ENG AERONAVEGACIÓ

GR ENG AEROPORTS

GR ENG SIS TELECOMUN

GR ENG SIST AEROESP

GR ENG TELEMÀTICA

MU AEROSPACE S&T 09

MU DRONS

MU MASTEAM 2009

MU MASTEAM 2015

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Calendari TFG de dipòsit i lectura

Documentació

Web UPC


 

Projecte llegit

Títol: Automatic Detection and Localization of Logic Gates using Image Recognition

Estudiants que han llegit aquest projecte:

Director: TARRÉS RUIZ, Francesc

Departament: TSC

Títol: Automatic Detection and Localization of Logic Gates using Image Recognition

Data inici oferta: 26-02-2013     Data finalització oferta: 26-10-2013


Estudis d'assignació del projecte:
    MU MASTEAM
Tipus: Individual
 
Lloc de realització: EETAC
 
Paraules clau:
Logic Gate, Integrated Circuit, Reverse Engineering, Image Processing, Matlab
 
Descripció del contingut i pla d'activitats:
In order to extract the images of a microchip is necessary attack the microchip with
mechanical or chemical lapping and taking pictures from the inside. The result is the
extraction of four layers with their respective images, including the cell layer where the
logic gates are defined. This image of the cell layer is very large and could store tens of
thousands of logic gates inside. The main objective of this project is to design and
implement a software to recognize logic gates and specify its precise location in the cell
layer of a microchip.
 
Overview (resum en anglès):
In order to extract the images of a microchip is necessary attack the microchip with
mechanical or chemical lapping and taking pictures from the inside. The result is the
extraction of four layers with their respective images, including the cell layer where the
logic gates are defined. This image of the cell layer is very large and could store tens of
thousands of logic gates inside. The main objective of this project is to design and
implement a software to recognize logic gates and specify its precise location in the cell
layer of a microchip.


Data de generació 26/01/2021