Projecte ofert
Títol: Modelling and Optimization of Hardware Clocks for Satellite Based Quantum Networks
Per assignar-vos el projecte us heu de dirigir al director/a perquè us l'assigni.
Director/a: JOFRE CRUANYES, MARC
Departament: ENTEL
Títol: Modelling and Optimization of Hardware Clocks for Satellite Based Quantum Networks
Data inici oferta: 09-05-2024 Data finalització oferta: 09-01-2025
Estudis d'assignació del projecte:
DG ENG AERO/SIS TEL- DG ENG AERO/TELEMÀT
- DG ENG SISTE/TELEMÀT
| Tipus: Individual | |
| Lloc de realització: EETAC | |
| Paraules clau: | |
| Quantum Communications, Satellite Quantum Networks, Hardware Clock | |
| Descripció del contingut i pla d'activitats: | |
| Quantum Networking (QN) has the potential to revolutionize many areas of science and technology [1], [2], [3]. Unlike the current Internet, which relies on classical bits, the quantum Internet will utilize quantum bits, or qubits, as its fundamental units of information. Qubits possess an extraordinary property known as superposition, enabling them to exist in a combination of 0 and 1 simultaneously. This unique feature grants qubits immense computational power, opening doors to applications that are currently beyond the reach of classical systems.
Moreover, QN are crucial components of the future quantum applications, enabling unprecedented quantum communication and computation capabilities within satellite distances [4]. However, the development of scalable and reliable QNs faces significant challenges, including the inherent fragility on time synchronization of quantum systems and the need for efficient integration with existing classical networking infrastructure. To address these challenges, this project proposes to evaluate a hardware clock system to be integrated in digital control boards, hereby utilizing advanced time measurement instruments to effectively model and evaluate its performance and scalability. In this direction, microcontroller cards will be employed due to their affordability, versatility, and programming flexibility, which serve as an ideal platform for implementing and modelling time synchronization architectures. Microcontrollers can replicate the functionality of QN nodes, enabling the emulation of quantum communication protocols and algorithms. Methodology and Objectives to achieve The approach of the project follows the Modern Timekeeping and Time Transfer [5] model which provides a standardized framework for designing and analyzing clock systems. Accordingly, the main objective of this research project is to model, optimize and characterize the temperature-controlled crystal oscillators clocks for satellite QNs. In particular, the clocks will be integrated in QN nodes' driving boards which emulate distributing signals throughout the network with a time synchronization specification compatible for quantum communications. The specific objectives of this research project are: - Model time hardware clocks for Quantum Networks. - Experimentally optimize and characterize the hardware clocks. - Characterize and discuss results, future work and limitations. Workplan First, at the modelling phase, the student will model hardware clocks with the direction of the directors of the thesis. At the optimization stage the candidate will have access to hardware equipment to configure and evaluate the clocks adjusted to QN for satellite systems. References [1] P. P. Rohde, The Quantum Internet: The Second Quantum Revolution. 2021. [2] H. J. Kimble, "The quantum internet," Nature, vol. 453, no. 7198, Art. no. 7198, Jun. 2008, doi: 10.1038/nature07127. [3] M. Pant et al., "Routing entanglement in the quantum internet," Npj Quantum Inf., vol. 5, no. 1, Art. no. 1, Mar. 2019, doi: 10.1038/s41534-019-0139-x. [4] R. V. Meter, Quantum Networking, 1st edition. London': Hoboken, NJ: Wiley-ISTE, 2014. [5] P. Banerjee and D. Matsakis, An Introduction to Modern Timekeeping and Time Transfer. in Springer Series in Measurement Science and Technology. Springer, 2023. |
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| Orientació a l'estudiant: | |
| Presencial | |
| Requereix activitats hardware: Si | |
| Horari d'atenció a estudiants per a l'assignació de projecte: Marc.jofre@upc.edu |
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