Projecte ofert
Títol: Development and Characterization of FPGA Time-to-Digital Systems for Quantum Networks
Per assignar-vos el projecte us heu de dirigir al director/a perquè us l'assigni.
Director/a: JOFRE CRUANYES, MARC
Departament: ENTEL
Títol: Development and Characterization of FPGA Time-to-Digital Systems for Quantum Networks
Data inici oferta: 11-05-2025 Data finalització oferta: 11-01-2026
Estudis d'assignació del projecte:
DG ENG AERO/SIS TEL- DG ENG SISTE/TELEMÀT
| Tipus: Individual | |
| Lloc de realització: EETAC | |
| Paraules clau: | |
| FPGA, Time-to-Digital Converter (TDC), Xilinx Zynq, MicroZed 7010, Quantum Networks, AXI Interconnect, Picosecond Timing | |
| Descripció del contingut i pla d'activitats: | |
| Description
Quantum Networks (QNs) require ultra-precise event timestamping to synchronize photon detections for secure quantum communication [1], [2]. This work presents an FPGA-based TDC implemented on the Xilinx MicroZed 7010 Zynq SoC, combining the high-speed processing capabilities of the Programmable Logic (PL) with the flexibility of the ARM-based Processing System (PS). The system uses AXI interconnect logic to efficiently transfer time-stamped quantum detection events from the PL to the PS, enabling real-time processing for secure communications, quantum teleportation, and entanglement distribution [3]. This approach ensures seamless integration between quantum hardware and classical processing, making it ideal for field-deployable quantum networks. The system's reconfigurability allows for adaptation to different quantum protocols, providing a versatile timing solution for both research and commercial quantum communication systems. Methodology and Objectives to achieve This research focuses on developing a Zynq-based TDC system that efficiently bridges quantum detection events with classical processing via AXI interconnect. The specific objectives of this research project are: - Design and implement a picosecond-resolution TDC in the PL of the MicroZed 7010. - Optimize AXI-based data transfer between PL and PS to minimize latency and ensure real-time processing of quantum detection events. - Characterize and discuss results, future work, and limitations. Workplan First, at the design phase, the student will have access to the application notes and manuals of the hardware components and knowledge from the directors of the thesis. At the development stage the candidate will have access to a laboratory equipped with instrumentation and components to conduct the hardware design (by understanding the involved fundamental concepts), assembly of the devices and evaluation of their performance. In parallel, the student will advance the writing of the Thesis in an ongoing effort through the estimated duration of the thesis (a semester). References [1] R. V. Meter, Quantum Networking, 1st edition. London': Hoboken, NJ: Wiley-ISTE, 2014. [2] O. Ezratty, "Understanding Quantum Technologies 2024," Nov. 06, 2024, arXiv: arXiv:2111.15352. doi: 10.48550/arXiv.2111.15352. [3] J. Johnson, "MicroZed," FPGA Developer. Accessed: May 11, 2025. [Online]. Available: https://www.fpgadeveloper.com/boards/microzed/ For further information contact: Prof. Marc Jofre: marc.jofre@upc.edu |
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| Orientació a l'estudiant: | |
| It is required that the student starts writing the project report from the beginning of the work, regularly submitting the progress to the directors in the regular meetings. The work is designed to be completed during a semester in the laboratory with constant dedication and approximately four hours a day. | |
| Requereix activitats hardware: Si | |
| Requereix activitats software: Sí Sistema operatiu: Linux Disc (Gb): | |
| Horari d'atenció a estudiants per a l'assignació de projecte: |
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